Frequency meter

ABSTRACT

A frequency monitor for giving a meter indication of the frequency of a signal utilizes a zero-crossing detector to control the counting of clock pulses to a pair of cascaded binary counters. The first counter covers the bulk of the period between zero crossings and the second counter covers the remainder thereof. The count in the second counter is periodically stored and fed to a digital-to-analog converter which includes means for performing an analog linearization of currents which energize a meter; such meter being calibrated in Hertz per unit current.

United States Patent Herbst 51 Nov. 28, 1972 [54] FREQUENCY NIETER3,227,952 1/1966 Proebster et al ..324/79 D [72] Inventor: John A.Herbst, Morristown, NJ.

Primary Examiner-Alfred E. Smith [73] Assrgnee: Bogue ElectricManufacturing Com- Att0mey phi1ip G. Hilbert pany, Paterson, NJ.

221 Filed: Jan. 18, 1971 1 V ABSTRACT 2 AppL 07 010 A frequency monitorfor giving a meter indication of the frequency of a signal utilizes azero-crossing detector to control the counting of clock pulses to a pairof [52] US. Cl. ..324/79 D, 324/78 J cascaded binary counters The firstcounter covers the ..G01l G011 of the between zero crossings and the[58] Md 0 Search 13 2 1 second counter covers the remainder thereof. TheI l9 92 count in the second counter is periodically stored and fed to adigital-to-analog converter which includes [56] References Clted meansfor performing an analog linearization of cur- UN STATES PATENTS rentswhich energize a. meter; such meter being calibrated in Hertz per unitcurrent. 2,844,790 7/ 1958 Thompson et a1 ..23S/92 T I 3,509,484 4/ 1970Basse. ..324/78 D 10 Clains, 2 Drawing Figures REFERENCE FREQUENCYSOURCE m l INPUT ZERO 5 1 AND CROSSING GATE gflci i J DETECTOR o 'E g ll AND I L 25 I AND I GATE 92 I I c o C 52 rn J 1 I COU'LNTER i L ggf I lR g R Q QZHHQN I L m c M58 T L T I ANALOG 7 E'cfifr ai'fiiioa ff "1 I mgi I leg lz 0 m l ll 01 L5? I PATENTEDnnv 28 I972 sum 2 or 2 FREQUENCYMETER BACKGROUND OF THE INVENTION This invention pertains to apparatusfor measuring and monitoring the frequency of periodic waveforms,commonly known as frequency meters.

Devices of this type in common usage fall into two classes; one of whichuses some type of resonant device, such as a tuned inductor-capacitornetwork, or a mechanically tuned reed. The other class of devices countthe number of cycles occurring within a carefully measured timeinterval. Devices in both classes have certain deficiencies.

Thus, resonant devices using tuned networks are slow in response and asensitivity to both voltage and harmonic distortion of the waveformbeing measured. Additionally, for precision accuracy, care must be givento the temperature-reactance effects of both the inductor and thecapacitor. With the tuned reed devices, the resolution is limited, andagain, temperature effects will be noted due to expansion coefficientsand temperature induced variations in mechanical stiffness.

With the counter type devices, the deficiency lies in respect to speedof response when accuracy is desired. Thus, if it is desired to measurea 400 Hertz alternating waveform to a 0.1 Hertz resolution, a count baseof at least seconds is required. If the frequency is changing, theaccuracy disappears, since the device only indicates that a certainnumber of cycles have occurred in the past, which may or may not be thecurrent rate. In addition, if the device is used as a monitor formanually making changes in frequency, the slowness of response isobjectionable.

It is therefore, a general object of the invention to provide animproved frequency meter for displaying, in analog form, the frequencyof a periodic waveform.

Another object of this invention is to provide a frequency meter whichis unaffected by the wave shape or harmonic content of the periodicwaveform.

A further object of the invention is to provide a frequency meter whichis relatively unaffected by the amplitude of the periodic waveform.

Still a further object of this invention is to provide a meter of thecharacter described, whose response to changes in rate of the periodicwaveform is detected within one cycle and displayed immediately.

Yet another object of this invention is to provide a meter of thecharacter described having means which effectively expands the trailingportion of the periodic waveform to give high precision measurement withminimum complexity.

Yet a further object of this invention is to provide a highly linearfrequency meter which measures the period of the input signal andconverts the period to a frequency indication.

Other objects of this invention will in part be obvious and in parthereinafter pointed out.

Briefly, the invention contemplates apparatus for measuring thefrequency of a periodically recurring signal by measuring the time forone period of the signal. The apparatus includes means for indicatingthe start of each cycle of the signal, a source of pulses having afrequency very much higher than the frequency of the signal, and firstand second pulse counters.

Switching means which includes first means responsive to the start ofcycle indicatingmeans, control the switching means to connect the pulsesource to the input of the first counter at the start of each cycle andsecond means connect the pulse source to the input of the second counterwhenever the first counter accumulates a predetermined count.

A count memory means is controlled to store the count in the secondcounter at the start of each cycle of the periodically recurring signal.Means connected to the memory means convert the stored pulse count to ananalog representation of the frequency of the periodically recurringsignal.

DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of the frequencymeter embodying the invention; and

FIG. 2 is a block diagram of the digital-to-analog conversion, includingthe feedback means for linearizing the reciprocal of the actualmeasurement made.

DESCRIPTION OF THE PREFERRED EMBODIMENTS In FIG. 1 there is shown afrequency monitoring system wherein the period of each cycle of aperiodic waveform from input frequency source IFS is measured bycounting in time-to-pulse count generator TPG, the number of clockpulses from reference source RFS that occur in each cycle of theperiodic waveform. This pulse count is stored in a memory and updated atthe termination of each cycle.

Thus, the output of the memory always shows the clock pulse count of theimmediately preceeding cycle. This digital count is fed to an analogfrequency indicator AFI.

Although the system can monitor many kinds of periodically recurringwaveforms, the following specific example will be illustrative thereof.To aid in understanding the operating principals, it will be assumedthat it is desired to display the actual frequency of a nominal 400Hertz generating system, with a frequency range of 390 to 410 Hertz, anda resolution of 0.1 Hertz.

It has been found that the design should be based on a somewhat largerspan than the actual meter range, so that the out-of-range conditionscan easily be detected. The calculations will therefore be on the basisof 389 to 411 Hertz. The actual time for 389 Hertz is 2,570.7microseconds per cycle, and for 411 Hertz is 2,433.1 microseconds percycle. The actual time span of interest is 2,570.72,433.1, or l37.6microseconds. I

The first problem is to select a clock frequency for the referencefrequency source RFl. Since the desired resolution is 0.1 in 20 Hertz,or one part in 200, the clock frequency should give at least 200 countsin 137.6 microseconds. Also, since the stable reference is asynchronouswith regard to the 400 Hertz input, an ambiguity of one count exists. Itis therefore desirable to double the number of counts to 400.

According to the invention, two counters should be used. Since it isdesirable to have the first counter a simple binary device, using ifpossible, a power of 2 for its count, the first counter should count to2 or 8,192 in 2,433.1 microseconds. Therefore, the required frequency is8,192 divided by 2433.1 x 10' which equals 3.36700 megahertz.

The total count for 389 Hertz is therefore 3,36700 times 2,570.7 or8,656 counts. Since the first counter counts 8,192, the secondcounterwill receive 8,656 minus 8,192 or 464 counts, which satisfies the400 count criterion. This counter must therefor be designed for 2 or 12counts.

With this set of parameters, the operation of the apparatus shown inFIG. 1, will be described. The input frequency source IFS is connectedtoa zero crossing detector ZD. Such detector can comprise a high gainamplifier, whose output is differentiated by a resistorcapacitor networkto give a narrow, sharp pulse at the beginning of each cycle.

The output of detector ZD is connected to set input 8 of latch L 1 whoseset or 1 output is connected to one input of two-input AND-gate G l andwhose reset or 0 output is connected to one input of two-input AND-gateG 2. The output of AND-gate G l is connected to the input of counterK 1. The other input of each of the AND gates is connected to referencequartz crystal osscillator of the type used in many digital systems issuitable for this purpose. The accuracy of the frequency measurement isdependent on the stability of the source RFS. Stability of sufficientlyhigh degree is readily attained with this type of oscillator.

Thus, when latch L l is set, AND-gate G 1 is open and AND-gate G 2 isblocked. Accordingly, the pulses from source RFS are fed to counter K 1Counter K 1 is provided with an output Q which emits a pulse when 8,192pulses have been accumulated and with an output Q/2 which emits a pulsewhen 4,096 pulses have been accumulated. The output Q is connected tothe reset input R of latch L 1 and the output Q/2 is connected to resetinput R of counter K 2. Thus, when 4,096 pulses have been accumulated,counter K 2 is set to zero and all of its inputs Q l to Q N go to zero.Each of the outputs of counter K 2 is connected to a different input ofNAND-gate G 4. 1

The output of NAND-gate G 4 is connected to one input of two-inputAND-gate G 3 whose other input is connected to the output of AND-gate G2. The output of AND-gate G 3 is connect ed to the input of counter K 2.Thus, only when the capacity of counter K 2 has not been exceeded, canpulses enter counter K 2. This prevents erroneous overflow of thecounter.

In any event, when the count in counter K 1 reaches 8,l92, latch L 1 isreset, and AND-gate G l is blocked, and AND-gate G 2 is opened. Now thepulses from source RFS are counted by counter K 2.

At the end of the cycle, which is also the beginning of the next cycle,the zero crossing detector ZD emits a to corresponding inputs 1 1 to l Nof the memory M.

The memory M can comprise nine bistable elements, with strobing meansfor setting the elements to the input states, and output connections foreach element. The pulse from the detector ZD energizes the strobe AFl',which performs the conversion of this digital information to an analogvoltage and displays the same on a D C meter. The indicator AFIcomprises a D C meter M driven by a digital-to-analog converter withcontrol and linearization circuits. In particular, such convertercomprises an analog gate AG 1 to AG N for each binary digit, withsuitably graded resistors, so that a fixed input voltage is converted toa current whose magnitude is a linear function of the digital number.

This is accomplished by making the resistors Rd 1, Rd 2 Rd n double invalue as their significance decreases. Thus, resistor Rd 1, the leastsignificant bit resistor, is twice the value of resistor Rd 2.

Since the highest frequency of interest is the shortest time per cycle,counter K 2 will receive no pulses and stay in the reset condition.However, conventionally, the meter M should read full scale for thiscondition. it is therefore preferable to connect the memory M to thedigital-to-analog converter so that in this case, the switches AG 1 toAG N are all in the closed condition. Consequently, the output currentis at maximum. As the frequency decreases, the counter K 2 exhibits ahigher count, selectively turning off the digital switches AG 1 to AG N,thus causing the output current to decrease.

Operational amplifier 0A 1 having a feedback resistor R 2, receives a DC voltage from a stable source via a resistor R 1 at its invertinginput 1. By proper selection of resistors R 1 and R 2, this voltage isconverted into a voltage suitable for the operation of thedigital-to-analog converter. The purpose of this conversion is to give asumming point at input I, where the linearization voltage may beinjected, as will hereinafter be described.

Operational amplifier OA 2 is used for zero output adjustment. It isdesirable that 390 Hertz read as zero volts on meter M. However, a390-cycle period equals 2.5641 microseconds, equal to 8,632 counts atthe chosen clock frequency. This would put 8,632 8,192, or 440 countsinto counter K 2. Since zero for the digital-to-analog converter is 2 or512 hits, the output would be 512 440 or 72 bits above zero.

Operational amplifier 0A 2 inverts the input voltage, changing itsabsolute value if desired for design reasons of selection of resistors R4 and R 5, and applies it to resistor R 6. By adjusting resistor R 6, anegative current equal to the digital-to-analog converter positiveoutput at 72 bits may be added to the output, forcing the current for390 Hertz as seen by amplifier OA 3 to be zero, thus giving a zerooutput to the meter M.

Operational amplifier OA 3 converts the current supplied by thedigital-to-analog converter to a voltage suitable for operating themeter M. The actual voltage may be set by adjusting the value ofresistor R 7.

Resistors R 6 and R 7 form adjusting points, whereby minor variations inclock frequency, stable D.C. source, etc., may be compensated. Byfeeding a stable 390 Hertz input, the zero point of meter M may be setby adjusting resistor R 6, and by feeding a stable 4l0 Hertz input, thefull scale reading may be set by adjusting resistor R 7.

The frequency meter described so far is not linear with respect tofrequency because a period has been measured and the frequency isinversely related to the period. In order to obtain an output which islinear with respect to frequency, a circuit is provided to inject aportion of the output signal into the input signal. In other words, apositive feedback having a particular value is required.

Thus, the output of operational amplifier .OA 3 is connected viafeedback resistor R 3 to the input I of operational amplifier OA 1.Since the output of operational amplifier 0A 3 is in phase with theinput of operational amplifier 0A 1, the feedback is positive asrequired. It can be shown that the positive feedback factor must beequal to B A/k2, where A is the frequency range to be covered, f f andk2 is a proportionality factor in ohms per unit time multiplied by theratio of f to f,,,,,,.

lclaim:

1. Apparatus for measuring the frequency of a periodically recurringsignal comprising means for indicating the start of each cycle of theperiodically recurring signal, a source of pulses having a frequencymuch higher than the frequency of the periodically recurring signal,first and second pulse counters, switching means for controllablyconnecting said source of pulses alternately to said first and secondpulse counter, said switching .means including first means responsive tosaid start of cycle indicating means to control said switching means toconnect said source of pulses to the input of said first counter at thestart of each cycle, and second means responsive to said first counterto connect said source of pulses to the input of said second counterwhenever the pulse count in said first counter reaches a predeterminedvalue, a count memory means connected to the output of said secondcounter for controllably storing the pulse count in said second counter,means connected to said indicating means for controlling said countmemory means to store the count in said second counter at the start ofeach cycle of the periodically recurring signal, and

means connected to said count memory means for converting the storedpulse count of said second counter to a linear analog representation ofthe frequency of the periodically recurring signal.

2. Apparatus as in claim 1 wherein said switching means comprises: alatch having a set input, a reset input, a set output, and a resetoutput; a first two-input AND-gate; and a second two-input AND-gate,means for connecting the output of said indicating means to the setinput of said latch, means for connecting a particular output of saidfirst counter to the reset input of said latch, means for connecting theset output of said latch to one input of said first two-input AND-gate,means for connecting the reset output of said latch to one input of saidsecond two-input AND-gate, means for connecting the output of saidsource of pulses to the second input of each of said two-inputAND-gates, means for connecting the output of said first two-inputAND-gate to the input of said first counter and means for connecting theoutput of said second two-input AND-gate to the input of said secondcounter.

3. Apparatus as in claim 2 wherein each of said counters has a clearinginput and further comprising means connected to the clearing input ofsaid first counter for clearing said first counter whenever the counttherein reaches said predetermined value and means connected to theclearing input of said second counter for clearing said second counterwhenever the count in said first counter reaches a particular valuewhich is less than said predetermined value..

4. Apparatus as in claim 2 wherein said means for connecting the outputof said second two-input AND- gate to said second counter comprises athird two-input AND-gate and a multi-input NAND-gate, means forconnecting the output of said second two-input AND- gate to one input ofsaid third two-input AND-gate, means for connecting the output of saidthird two-input AND-gate to the input of said second counter, means forconnecting the output of said multi-input NAND- gate to the second inputof said third two-input AND- gate, and means for connecting each of theinputs of said multi-input NAND-gate to a different one of the outputsof said second counter. v

5. The apparatus of claim 4 wherein each of said counters has a clearinginput and further comprises means connected to said clearing input ofsaid first counter for clearing said first counter whenever the counttherein reaches said predetermined value and means connected to theclearing input of said second counter for clearing said second counterwhenever the count in said first counter reaches a particular valuewhich is less than said predetermined value.

6. The apparatus of claim 1 wherein said means for converting the storedcount to an analog representation comprises an input amplifier forgenerating an input current, a digital-to-analog converting means forscaling said input current to values inversely related to the digitalrepresentation of the stored pulse count, an output amplifier having aninput for receiving the scaled current and an output transmitting asignal proportional to the received scaled current and means connectedto the output of said output amplifier for converting the signaltherefrom to a linear visual representation of the frequency of a periodrecurring signal.

7. The apparatus of claim 6 wherein said input amplifier is anoperational amplifier having an input and further comprising feedbackmeans for connecting the output of said output amplifier to the input ofsaid input amplifier.

8. The apparatus of claim 7, further comprising an inverting currentamplifier connecting the output of said input amplifier to the input ofsaid output amplifier in parallel with said digital-to-analog convertingmeans for zero adjusting the scaled current received at the input ofsaid output amplifier.

9. The apparatus of claim 4 wherein said means for converting the storedcount to an analog representation comprises an input amplifier forgenerating an input 10. The apparatus of Eii-i's wherein said inputamplifier is an operational amplifier having an input and furthercomprising feedback means for connecting the output of said outputamplifier to the input of said input amplifier, and an inverting currentamplifier connect-

1. Apparatus for measuring the frequency of a periodically recurring signal comprising means for indicating the start of each cycle of the periodically recurring signal, a source of pulses having a frequency much higher than the frequency of the periodically recurring signal, first and second pulse counters, switching means for controllably connecting said source of pulses alternately to said first and second pulse counter, said switching means including first means responsive to said start of cycle indicating means to control said switching means to connect said source of pulses to the input of said first counter at the start of each cycle, and second means responsive to said first counter to connect said source of pulses to the input of said second counter whenever the pulse count in said first counter reaches a predetermined value, a count memory means connected to the output of said second counter for controllably storing the pulse count in said second counter, means connected to said indicating means for controlling said count memory means to store the count in said second counter at the start of each cycle of the periodically recurring signal, and means connected to said count memory means for converting the stored pulse count of said second counter to a linear analog representation of the frequency of the periodically recurring signal.
 2. Apparatus as in claim 1 wherein said switching means comprises: a latch having a set input, a reset input, a set output, and a reset output; a first two-input AND-gate; and a second two-input AND-gate, means for connecting the output of said indicating means to the set input of said latch, means for connecting a particular output of said first counter to the reset input of said latch, means for connecting the set output of said latch to one input of said first two-input AND-gate, means for connecting the reset output of said latch to one input of said second two-input AND-gate, means for connecting the output of said source of pulses to the second input of each of said two-input AND-gates, means for connecting the output of said first two-input AND-gate to the input of said first counter and means for connecting the output of said second two-input AND-gate to the input of said second counter.
 3. Apparatus as in claim 2 wherein each of said counters has a clearing input and further comprising means connected to the clearing input of said first counter for clearing said first counter whenever the count therein reaches said predetermined value and means connected to the clearing input of said second counter for clearing said second counter whenever the count in said first counter reaches a particular value which is less than said predetermined value.
 4. Apparatus as in claim 2 wherein said means for connecting the output of said second two-input AND-gate to said second counter comprises a third two-input AND-gate and a multi-input NAND-gate, means for connecting the output of said second two-input AND-gate to one input of said third two-input AND-gate, means for connecting the output of said third two-input AND-gate to the input of said second counter, means for connecting the output of said multi-input NAND-gate to the second input of said third two-input AND-gate, and means for connecting each of the inputs of said multi-input NAND-gate to a different one of the outputs of said second counter.
 5. The apparatus of claim 4 wherein each of said counters has a clearing input and further comprises means connected to said clearing input of said first counter for clearing said first counter whenever the count therein reaches said predetermined value and means connected to the clearing input of said second counter for clearing said second counter whenever the count in said first counter reaches a particular value which is less than said predetermined value.
 6. The apparatus of claim 1 wherein said means for converting the stored count to an analog representation comprises an input amplifier for generating an input Current, a digital-to-analog converting means for scaling said input current to values inversely related to the digital representation of the stored pulse count, an output amplifier having an input for receiving the scaled current and an output transmitting a signal proportional to the received scaled current and means connected to the output of said output amplifier for converting the signal therefrom to a linear visual representation of the frequency of a period recurring signal.
 7. The apparatus of claim 6 wherein said input amplifier is an operational amplifier having an input and further comprising feedback means for connecting the output of said output amplifier to the input of said input amplifier.
 8. The apparatus of claim 7, further comprising an inverting current amplifier connecting the output of said input amplifier to the input of said output amplifier in parallel with said digital-to-analog converting means for zero adjusting the scaled current received at the input of said output amplifier.
 9. The apparatus of claim 4 wherein said means for converting the stored count to an analog representation comprises an input amplifier for generating an input current, a digital-to-analog converting means for scaling said input current to values related to the digital representation of the stored pulse count, an output amplifier having an input for receiving the scaled current and an output transmitting a signal proportional to the received scaled current and means connected to the output of said output amplifier for converting the signal therefrom to a visual representation.
 10. The apparatus of claim 9 wherein said input amplifier is an operational amplifier having an input and further comprising feedback means for connecting the output of said output amplifier to the input of said input amplifier, and an inverting current amplifier connecting the output of said input amplifier to the input of said output amplifier in parallel with said digital-to-analog converting means for zero adjusting the scaled current received at the input of said output amplifier. 